Improved Performance of Ultra-Thin HfOz CMOSFETs Using Poly-SiGe Gate

Poly-SiGe is investigated as the gate material for CMOS transistors with ultra-thin Hf02 gate dielectric. Compared with polySi, poly-SiGe reduces the gate depletion effect, and also results in thinner EOT of the gate dielectric after 1000°C annealing, with low gate leakage maintained. The Si interface quality is also better than that achieved with surface nitridation, which has been used to reduce EOT. Therefore, the use of poly-SiGe as the gate material is effective for improving the performance of ultra-thin Hf02 CMOS transistors. INTRODUCTION Continued CMOS scaling will require high-k gate dielectrics to achieve low gate leakage and thin equivalent oxide thickness (EOT). While the most promising high-k material has yet to be determined, the preferred gate electrode material is clearly poly-Si, for simplicity in process integration. HfOz has been proposed as a very promising high-k gate dielectric candidate, and is relatively stable with poly-Si gate. In previous studies, the anneal temperature of the poly-Si/HfOz gate stack has been limited to 950°C or below, which is not adequate for minimizing the poly-Si gate depletion effect. Higher annealing temperatures result in increased EOT and gate leakage [I]. In order to make Hf02 viable for a state-of-the-art CMOS process, it is essential that thin EOT and low leakage be maintained after sufficiently high temperature annealing processes so as not to compromise device performance. Poly-SiGe is known to alleviate the gate depletion problem and to reduce boron penetration, and it can be readily integrated into conventional CMOS processes [2]. Therefore, if poly-SiGe gate is thermally stable with Hf02 gate dielectric, improved device performance can be achieved with lower thermal budget, which also helps to reduce EOT and gate leakage. Recently, it was reported that surface nitridation of Si prior to Hf02 deposition is effective for achieving ultra-thin EOT and suppressing boron penetration [3]. In this work, this technique is compared with the approach of using poly-SiGe as the gate material to reduce EOT. To test the suitability of HfO2 to modern CMOS processes, aggressive annealing at 1000°C was used in device fabrication. DEVICE FABRICATION Transistors were fabricated using an n-well CMOS process. After LOCOS processing, the Si substrates received an HF clean, then four gate stack structures were formed, as detailed in Fig. 1. Prior to HfOz deposition, surface nitridation in NH3 was applied to some wafers to form the bottom nitride layer. In all cases, the physical thickness of the sputter-deposited Hf02 layer was the same. Undoped polySi0.75Ge0.25 or Si gate was then deposited by LPCVD at 550°C. After gate patterning, implantations for nand pS/D extensions were performed, followed by low temperature oxide (LTO) spacer formation. After n+ S/D implantation, the wafers were annealed at 800°C for 30 min. A rapid thermal anneal (RTA) of 1000°C 10 s was applied after pf S/D implantation. Devices were finished with LTO passivation, contact formation, metallization and forming gas anneal. RESULTS AND DISCUSSION N-FET C-V characteristics are compared in pairs to elucidate the effect of using poly-SiGe gate (Fig. 2) and the effect of using surface nitridation (SN) (Fig. 3). EOTs were extracted using a quantum C-V simulator that takes into account gate depletion effect [4]. Poly-SiGe 86 0-7803-7312-X/02/$17.00 02 02 IEEE gate yields thinner EOT than poly-Si gate, but the difference is smaller with SN. SN provides thinner EOT for poly-Si gate, but not for poly-SiGe gate. These results indicate that the use of poly-SiGe as the gate material suppresses the formation of an interfacial layer at the Si surface because SiGe is a good diffusion barrier for oxygen, as is the bottom nitride layer. The precise cause of the effect of polySiGe gate is presently under investigation. As poly-SiGe gate already has the effect of reducing EOT, the extra nitride layer which is grown at the Si interface during the SN treatment results in a slightly larger EOT for poly-SiGe gate (Fig. 3a). The higher inversion capacitances of the poly-SiGe gated devices in Fig. 2 indicate that the active dopant concentration is higher in poly-SiGe than in poly-Si, resulting in reduced gate depletion. Cross-sectional transmission electron microscopy (TEM) gate-stack images of poly-Si or poly-SiGe gate with SN are shown in Fig. 4, for devices that received 950°C 30 s RTA. The device with SiGe gate shows a slightly thinner interfacial layer, while C-V measurements indicate that two gate stacks have similar EOT. The larger difference in EOT seen in Fig. 2b suggests that there is a larger difference in the interfacial layer thickness in Sivs. SiGe-gated devices after 1000°C RTA. The gate leakage currents of the four types of gate stacks are shown in Fig. 5. It can be seen that overall the leakages remained low after the 800°C 30 min + 1000°C 10 s anneal, and that the leakage current is more sensitive to SN than to the gate material. The higher leakage for the SiGe-gated device without SN is likely due to the thinner EOT. For a given EOT, N-FETs have higher leakage than PFETs due to much higher potential barrier for holes [5]. When plotted against EOT (Fig. 6), these data roughly follow the empirical trend line from literature [6]. Therefore, the use of SiGe gate preserves the low leakage benefit of Hf02. Ramp breakdown tests on these devices showeid that the breakdown voltage VBD is improved by SN, but is insensitive to the gate material, possibly because the limiting factor in dielectric damage is the hole injection from the gate, which is reduced by the higher barrier for a. nitride layer. Even without SN, the VBD’S of Si or SiGe gated devices appear to be sufficient for future Iow-VDD operations [7] Due to thinner EOT and possibly better interface quality, transistors with SiGe gate and no SN showed higher drive current than those with Si gate and SN (Fig. 8), which has high interface trap density. This suggests that SiGe gate is an effective technique in addition to SN to improve the performance of HfO2 MOSFETs. Preliminary carrier mobility data indicates that the devices with SiGe gate and no SN have higher mobility than those with Si gate and SN under the same effective electrical field, but still lower than the universal mobility model for Si02. This suggests that there is minimal SiOl like interfacial layer formed with SiGe gate, consistent with the thinner EOT and higher gate leakage current than devices with SN. CONCLUSION Poly-SiGe is studied as the gate material for HfO2 gate dielectric. It is found to improve device performance through not only enhanced gate dopant activation, but also the reduction of EOT and possibly better interface quality. Therefore, it is an attractive gate material for use with Hi02 gate dielectric in future CMOS technologies.